Asynchronous Circuit Design & Test – A Tutorial

Silicon technologies advances brought the possibility of integrating billions of transistors in a VLSI die. However, as these transistors become smaller due to fabrication method enhancements, some aspects that were negligible in older technologies emerge as difficulties for the design in current and future technology nodes. In this context, fully synchronous digital circuits become harder to build and test. For example, clock distribution may become an overwhelming design problem. Also, variability issues may require margins that render synchronous implementations prohibitive or very expensive. Asynchronous or clock-less design paradigms recently attracted new interest from research communities, due to their improved ability to cope with issues like design timing closure and variability. This tutorial approaches the most relevant traditional and modern methods for the design and test of asynchronous digital circuits. The emphasis is on the infrastructure required to support the design of such circuits, conditioned to a chosen design method.